m255
o
cModel Technology
dC:\Xilinx\projects\20x6_Processor
vadd16bit
IC]ihZ5=9LOkXO_[hRDA`D0
V5A57@17=8^<;VI=DBGio;2
dC:\Xilinx\Projects\20x6_Processor
w1068873948
Fadd16bit.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vaddr_select
I]_]dW9N4`4eE9F?d3c>@?1
VEl9Q9adSWIBR1`:X_94=Q3
dC:\Xilinx\Projects\20x6_Processor
w1068873821
Faddr_select.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
valu16bit
I?WYBVM8kHFlblF9dZ:6W21
VFZcfe:;aAKR?0=?h<<KTf0
dC:\Xilinx\Projects\20x6_Processor
w1068960422
Falu16bit.vf
L0 66
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
valuone
I0OOYmZ`<E?TU`j7NdjWzE1
V0YD3noD;h]25@[ZKUkDlb1
dC:\Xilinx\Projects\20x6_Processor
w1068933556
Faluone.vf
L0 73
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vbus_mux1
IzLNE0IS?Ed:^U0G]CTEC_1
Vfc<`MC`F<a[@9;ZW0S43K2
dC:\Xilinx\Projects\20x6_Processor
w1068870564
Fbus_mux1.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vbusconcat
I>:?Tm[Kkb`>FFUo1_`JIX1
V_Ba^_UMLe7GZ<HRFC=G:K0
dC:\Xilinx\Projects\20x6_Processor
w1068933558
Fbusconcat.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vbusthing
IWj^3Y[YANV<T2de_nAhCP3
V[aN;TzB`BP>MWW=7_FO@30
dC:\Xilinx\Projects\20x6_Processor
w1068933572
Fbusthing.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vbusthingy
IS=?^Y]_jZKH72S66<@`<70
V9>:fKLPMj3>AO?@Go:m3e0
dC:\Xilinx\Projects\20x6_Processor
w1068933574
Fbusthingy.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vByteRam
IMP[1I6WT^m[BEIja_95h<1
Va:[BQ7j^JB]hUdSH2cD]A1
dC:\Xilinx\Projects\20x6_Processor
w1069134888
FbyteRAM.v
L0 36
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@byte@ram
vclkdivider
IWzmSbZgjd4W@a4]zLVi?]0
VGZ6QCZe0LzCRGE]1o]]g>3
dC:\Xilinx\Projects\20x6_Processor
w1068937190
Fclkdivider.v
L0 1
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vclock_divider2
Io3XLI>>Y@5=TPjBHoa4@R2
VAJ3LdI2f@o6_RI?kD7fI_0
dC:\Xilinx\Projects\20x6_Processor
w1069012855
Fclock_divider2.v
L0 1
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vcomparer
IRY3Ll08Pn85C[40>e=IM>1
V26I]fTB;DhRc8FV2MAPAI3
dC:\Xilinx\Projects\20x6_Processor
w1068933558
Fcomparer.vf
L0 55
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vconcat8x8
I3[5bnm1<NFf5MdIg6Boo>0
VLd8;8H1PYEUMf@PW;fiTj0
dC:\Xilinx\Projects\20x6_Processor
w1068933571
Fconcat8x8.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vcounter8
IY:kX0[IPJEm9]HboITW7B0
VQA7kb;?RSON4S@9JOgLjm0
dC:\Xilinx\Projects\20x6_Processor
w1068937584
Fcounter8.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdecode1
IQ0zn;VW_XJ8g2[PLLGbme0
VS]cg75`XZmbZPM[VVCKgX0
dC:\Xilinx\Projects\20x6_Processor
w1066792422
Fdecode1.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vDigitDisplay
Ice3GfD_C^WA;^jRg[lLcd3
V10PeNoC>L00RVPc5od3oP2
dC:\Xilinx\Projects\20x6_Processor
w1068843854
Fdigit_display.v
L0 3
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@digit@display
vdirtybusmux2
IbA[Pjj0e0gTKaTdzlMcNP3
VDiY>]EOMYX3CgY@28434z2
dC:\Xilinx\Projects\20x6_Processor
w1068872948
Fdirtybusmux2.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdirtybusmux2_4bit
Iin]8700k;jzOUgL3068cC3
VaW?j9Q@Tn>nL`Tm`Ye3Og3
dC:\Xilinx\Projects\20x6_Processor
w1068873060
Fdirtybusmux2_4bit.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdirtybusmux3_16bit
IjR>Vf:j4@i@f6OU9APSO52
V=f:kR6O]5cnkSE[96jLSA3
dC:\Xilinx\Projects\20x6_Processor
w1068873193
Fdirtybusmux3_16bit.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdirtybusmux3_4bit
IdJF87=Mb3;cBDEPg3dOVc3
VA_X;]74DD96``S?RHH8:?1
dC:\Xilinx\Projects\20x6_Processor
w1068873280
Fdirtybusmux3_4bit.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdirtybusmux4
IC9Qlk7OzfbznXGeUIX;jQ0
V4[bi<@CB63N^P1<60nj^=3
w1068260035
Fdirtybusmux4.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdirtybusmux5_16bit
I[;ziSc2oD:ibld5[_`SV82
VO2GdzgH[8UFlDRPJX2TjW1
dC:\Xilinx\Projects\20x6_Processor
w1068873363
Fdirtybusmux5_16bit.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdirtybusmux8
Ijof_F;;31<]0WgFh:X]YH0
V4^lfP]4S@bW7W2JL]PYcc0
dC:\Xilinx\Projects\20x6_Processor
w1068873508
Fdirtybusmux8.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdistrom
I3VnNDcnFgLGKk5=GYTmRh1
VUKe;`]]S1Lj3<[MD]EW141
dC:\Xilinx\Projects\20x6_Processor
w1068871843
Fdistrom.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vdistromv
I`eV;mFN[j_hnXO?Ei1kzm0
Vz^JShoi9PH;^[;g^]fEme1
dC:\Xilinx\Projects\20x6_Processor
w1068961747
Fdistromv.v
L0 1
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
veight_cycle_one_shot
I_;0EII3oeDI^iYJHVn@PB0
V6IWC=SiR7k=e<?Ck?GNOl3
dC:\Xilinx\Projects\20x6_Processor
w1069012779
Feight_cycle_one_shot.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vEightShot
II<a=TfNNBNzio3K8Q28H51
V`;YZXaSm[DRGI_a_MoC9K2
dC:\Xilinx\Projects\20x6_Processor
w1069011314
FEightShot.v
L0 1
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@eight@shot
vfinalregtest
I`9eKD^fO4^K5g3^6nm<a72
Voi=DBG0VOMk8Se0N?dDh10
dC:\Xilinx\Projects\20x6_Processor
w1068933559
Ffinalregtest.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vfulladd1
I>68HdRQln;`CNzm0UgG_20
V=olGaKWhagi[9dJ7lQ;gC2
dC:\Xilinx\Projects\20x6_Processor
w1068933557
Ffulladd1.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vglbl
IFAMRGAX`bCK2PK0fJAiGk2
VDbL]YG2GFhLmAAcPD`b9d2
dC:\Xilinx\Projects\20x6_Processor
w1039793798
FC:/Xilinx/verilog/src/glbl.v
L0 3
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vINV16_MXILINX_comparer
Iijf?_`oDk:>@Y0F:eiS1Q0
V7Z9LS_YjXV]QYcnhB73J`0
dC:\Xilinx\Projects\20x6_Processor
w1068933558
Fcomparer.vf
L0 26
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@i@n@v16_@m@x@i@l@i@n@x_comparer
vleftshifter
INk2i4C1B_BD6]n]<0P?ZH0
VbWH?Hm;mOD1[TUOlOVCNQ3
dC:\Xilinx\Projects\20x6_Processor
w1068933551
Fleftshifter.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vM16_1E_MXILINX_shifter
IIkJ:J2I;bSclNg5gbli7^2
Vj7J<2@?M3m[NOlGg_n1040
dC:\Xilinx\Projects\20x6_Processor
w1068933554
Fshifter.vf
L0 47
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@m16_1@e_@m@x@i@l@i@n@x_shifter
vM2_1_MXILINX_aluone
IoBfOISA`_=A^UK=>gfSAA2
VGiQZh1JVO8VCdYMD@JL:`0
dC:\Xilinx\Projects\20x6_Processor
w1068933556
Faluone.vf
L0 53
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@m2_1_@m@x@i@l@i@n@x_aluone
vM2_1_MXILINX_comparer
IXL_=eTEF?o1dfhXTVH`QG2
Vd7`OQf;@zgMH<;2YFi?:k2
dC:\Xilinx\Projects\20x6_Processor
w1068933558
Fcomparer.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@m2_1_@m@x@i@l@i@n@x_comparer
vM2_1_MXILINX_shifter
IUL6DN=GLlKI3Yfmn6E28h3
Vh]AI009J1bS[Y7>gJ6=@82
dC:\Xilinx\Projects\20x6_Processor
w1068933554
Fshifter.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@m2_1_@m@x@i@l@i@n@x_shifter
vM2_1E_MXILINX_aluone
IJ7Jz9bJ0Az^4KaFNkS:lY2
VVR6Elf2b?ZaA6H?CQFz7W2
dC:\Xilinx\Projects\20x6_Processor
w1068933556
Faluone.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@m2_1@e_@m@x@i@l@i@n@x_aluone
vM2_1E_MXILINX_shifter
I_l5FN33GTzN6S=5e8[F`^3
V>4NA4>b=19;a:]Al7BjVb2
dC:\Xilinx\Projects\20x6_Processor
w1068933554
Fshifter.vf
L0 26
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@m2_1@e_@m@x@i@l@i@n@x_shifter
vM4_1E_MXILINX_aluone
I@XBUM0G8]UDXON>8LSQTN0
V]b;U3_813:Mheo=k3c0Uk0
dC:\Xilinx\Projects\20x6_Processor
w1068933556
Faluone.vf
L0 27
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@m4_1@e_@m@x@i@l@i@n@x_aluone
vmux4
I]ciA^idFTZHkiM?DiLf=31
VOJVb[_90ADP@HbKddCYKU1
dC:\Xilinx\Projects\20x6_Processor
w1068874045
Fmux4.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vmux4x16
IaTK3JcLcX1`5mmMSE_HUz3
VC4<H>P6YhXAm81A2L7DZQ0
dC:\Xilinx\Projects\20x6_Processor
w1068933573
Fmux4x16.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vnewmemcore
Id7Uac`9B]A5ciWzCfRh@T0
V5i:bA]N@?_OU?@l1Cn^2>0
dC:\Xilinx\Projects\20x6_Processor
w1068884949
Fnewmemcore.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vNewMemory
IR=cNlDX:mcib?6b^FMa451
VQg_DQdo3;;28GFV8Y<oD03
dC:\Xilinx\Projects\20x6_Processor
w1068882048
FNewMemory.v
L0 1
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@new@memory
vnewmemorycore
IjA0TTeP:a9?M?W2=zJS981
V[[jZW2O>hWfGMX[@3Vk=m0
dC:\Xilinx\Projects\20x6_Processor
w1068884756
Fnewmemorycore.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vNOR16_MXILINX_alu16bit
I905;8QH^mBzGME9NYOD`30
VkQJan_9P<?d>R0HD[QHOc1
dC:\Xilinx\Projects\20x6_Processor
w1068960422
Falu16bit.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
n@n@o@r16_@m@x@i@l@i@n@x_alu16bit
vone_shot
Ik=0D3g5MA^KRfOQ6bmikO0
VC0iOLE0<Xh1KnWIfOYoTD2
dC:\Xilinx\Projects\20x6_Processor
w1068943128
Fone_shot.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vprocessor
IHJl1lS?e_Z@E`9kl?G7BU1
VF7DYTc^<eg[<fWzE805cg3
dC:\Xilinx\Projects\20x6_Processor
w1069135302
Fprocessor.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vramtest
IPFdRZBN]3G;9Bl<?BIcKB1
VNkiQ?:hTPXFZf1E274<YV1
dC:\Xilinx\Projects\20x6_Processor
w1068943201
Framtest.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vregister16bit
IHDdNLDJW:E1SE5kZR>:jQ0
V]=DEo[G[gD9@<m7BVcHh<1
dC:\Xilinx\Projects\20x6_Processor
w1068873641
Fregister16bit.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vregister16bitwrite
IhE;Q@QzzokDPC;BF6[[5n2
V[ieQ?9kOIPMODn^_?hGo>0
dC:\Xilinx\Projects\20x6_Processor
w1068873724
Fregister16bitwrite.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vregs
Ic5UD_IGeQTdoO80b@JVhc1
VZcUFX_YM0jZn3CIRWVV8E1
dC:\Xilinx\Projects\20x6_Processor
w1068933570
Fregs.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vregwclock
I<7_o9[RB6NX4G][=l`d1]3
VLH8d;L0SVa9NZ[B?6ReJk0
dC:\Xilinx\Projects\20x6_Processor
w1067282802
Fregwclock.v
L0 38
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vshifter
I@DfAPO?TJnDKS=A^Pla]c0
V78mUi0=fN@e63UcIiZH8n1
dC:\Xilinx\Projects\20x6_Processor
w1068933554
Fshifter.vf
L0 119
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vtestbench
Ion1h_644Bm@ce9f[lRm>R0
VhGfW:390DM[oDMzegDH9`2
dC:\Xilinx\Projects\20x6_Processor
w1069135291
Fproctest_tf.tf
L0 28
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
vxcontrol
IU_aEhMn<1=c<zzk<D^k]93
VGOdACdONVXc[]ZbjRSihi1
dC:\Xilinx\Projects\20x6_Processor
w1068961856
Fxcontrol.vf
L0 6
OX;L;5.6e;17
r1
31
o-93 +libext+.v+.ve+ +define+OVI_Verilog+ -O0
